/**
 * Verilog HDL
 * http://www.xilinx.com/itp/xilinx6j/help/iseguide/html/he_verilog_reserved_words.htm
 */

PR.registerLangHandler(
    PR.createSimpleLexer(
        [
         // Whitespace
         [PR.PR_PLAIN, /^[\t\n\r \xA0]+/, null, '\t\n\r \xA0']
        ],
        [
         // String, character or bit string
         [PR.PR_STRING, /^(?:[BOX]?"(?:[^\"]|"")*"|'.')/i],
         // Comment, from two dashes until end of line.
         [PR.PR_COMMENT, /^--[^\r\n]*/],
         [PR.PR_KEYWORD, /^(?:always|assign|begin|case|casex|casez|cell|config|deassign|default|defparam|design|disable|edge|else|end|endcase|endconfig|endgenerate|endmodule|endfunction|endprimitive|endspecify|endtable|endtask|event|for|force|forever|fork|function|generate|genvar|if|ifnone|initial|inout|input|instance|join|liblist|localparam|macromodule|module|negedge|noshowcancelled|output|parameter|posedge|primitive|pulsestyle_ondetect|pulsestyle_onevent|reg|release|repeat|scalared|showcancelled|signed|specify|specparam|strength|table|task|tri|tri0|tri1|triand|trior|wand|wor|trireg|unsigned|use|vectored|wait|while|wire)(?=[^\w-]|$)/i, null],
         // Type, predefined or standard
         [PR.PR_TYPE, /^(?:bit|bit_vector|character|boolean|integer|real|time|string|severity_level|positive|natural|signed|unsigned|line|text|std_u?logic(?:_vector)?)(?=[^\w-]|$)/i, null],
         // Number, decimal or based literal
         [PR.PR_LITERAL, /^\d+(?:_\d+)*(?:#[\w\\.]+#(?:[+\-]?\d+(?:_\d+)*)?|(?:\.\d+(?:_\d+)*)?(?:E[+\-]?\d+(?:_\d+)*)?)/i],
         // Identifier, basic or extended
         [PR.PR_PLAIN, /^(?:[a-z]\w*|\\[^\\]*\\)/i],
         // Punctuation
         [PR.PR_PUNCTUATION, /^[^\w\t\n\r \xA0\"\'][^\w\t\n\r \xA0\-\"\']*/]
        ]),
    ['verilog', 'ver']);